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512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module ( TSOP-II )
184pin Registered Module based on 512Mb B-die with 1,700 / 1,200mil Height & 72-bit ECC
Revision 1.0 December. 2003
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
Revision History
Revision 0.0 (February, 2003) - First release Revision 0.1 (July, 2003) - Deleted speed B3 Revision 0.2 (August, 2003) - Corrected typo. Revision 1.0 (December, 2003) - IDD current revision. - Finalized
DDR SDRAM
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
184Pin Registered DIMM based on 512Mb B-die (x4, x8)
Ordering Information
Part Number M383L6523BTS-CAA/A2/B0/A0 M383L2923BTS-CAA/A2/B0/A0 M383L2920BTS-CAA/A2/B0/A0 M383L5628BT1-CAA/A2/B0/A0 M312L6523BTS-CAA/A2/B0/A0 M312L2923BTS-CAA/A2/B0/A0 M312L2920BTS-CAA/A2/B0/A0 M312L5628BT0-CAA/A2/B0/A0 Density 512MB 1GB 1GB 2GB 512MB 1GB 1GB 2GB Organization 64M x 72 128M x 72 128M x 72 256M x 72 64M x 72 128M x 72 128M x 72 256M x 72
DDR SDRAM
Component Composition 64Mx8( K4H510838B) * 9EA 64Mx8( K4H510838B) * 18EA 128Mx4( K4H510438B) * 18EA st.256Mx4( K4H1G0638B) * 18EA 64Mx8( K4H510838B) * 9EA 64Mx8( K4H510838B) * 18EA 128Mx4( K4H510438B) * 18EA st.256Mx4( K4H1G0638B) * 18EA
Heihgt 1,700mil 1,700mil 1,700mil 1,700mil 1,200mil 1,200mil 1,200mil 1,200mil
Operating Frequencies
AA(DDR266@CL=2) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 133MHz 2-2-2 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3 A0(DDR200@CL=2) 100MHz 2-2-2
Feature
* Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * 1,700mil / 1,200mil height & double sided
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
Pin Configuration (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS *CK2 */CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7
DDR SDRAM
Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back /RAS DQ45 VDDQ /CS0 /CS1 DM5/DQS14 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
KEY
DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
KEY
VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44
Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 are NC for 1row module [ M383(12)L6523BTS, M383(12)L2920BTS ] & used for 2row module [ M383(12)L2923BTS, M383(12)L5628BT1(0) ] 3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0, CK0 CKE0, CKE1(for 2 Row) CS0, CS1(for 2 Row) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name DM0 ~ DM8 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power/Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM No connection Function
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
512MB, 64M x 72 ECC Module (M383(12)L6523BTS) Functional Block Diagram
RCS0 DQS0 DM0
DM/ CS DQS
DDR SDRAM
(Populated as 1 bank of x8 DDR SDRAM Module)
DQS4 DM4
DM/ CS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D4
DM/
CS
DQS
DM/
CS
DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D5
DQS2 DM2
DM/ CS DQS
DM/
CS
DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D6
DM/
CS
DQS
DM/
CS
DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
Serial PD D7 SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
V DDSPD
DM/ CS DQS
SPD D0 - D8 D0 - D8
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
V DD /VDDQ
D8
VREF VS S
D0 - D8 D0 - D8
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE
PCK PCK
R E G I S T E R
RCS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE
RESET
BA0 -BA1 : SDRAMs DQ0 - D8 A0 -A12 : SDRAMs D0 - D8 RAS : SDRAMs D0 - D8 CAS : SDRAMs D0 - D8 CKE : SDRAMs D0 - D8 WE: SDRAMs D0 - D8
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
1GB, 128M x 72 ECC Module (M383(12)L2923BTS) Functional Block Diagram
R C S1 R C S0 DQS0 DM0
DM/ CS DQS DM/ CS DQS
DDR SDRAM
(Populated as 2 bank of x8 DDR SDRAM Module)
DQS4 DM4
DM/ CS DQS DM/ CS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D0
I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
D9
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D4
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 6 7 2 3 4 5
D13
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D1
I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D5
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 6 7 2 3 4 5
D14
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D2
I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
D11
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D6
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 6 7 2 3 4 5
D15
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D3
I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
D12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
D7
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 6 7 2 3 4 5
D16
DM/
CS
DQS
DM/
CS
DQS
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O I/O I/O I/O I/O I/O I/O I/O
7 6 1 0 5 4 3 2
D8
I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
D17
Serial PD SCL WP A0 SA0 A1 SA1 A2 SDA
V DDSPD V DD /VDDQ
SPD D0 - D17 D0 - D17
VREF
D0 - D17 D0 - D17
SA2
VS S
CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1
WE
R E G I S T E R
RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE
RESET
BA0 -BA1 : SDRAMs DQ0 - D17 A0 -A12 : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS : SDRAMs DQ0 - D17 CKE : SDRAMs D0 - D8 CKE : SDRAMs D9 - D17 WE: SDRAMs D0 - D17
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
PCK PCK
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/ CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
1GB, 128M x 72 ECC Module (M383(12)L2920BTS) Functional Block Diagram
VSS RCS0 DQS0
D0 Q D1 Q D2 Q D3 Q DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DDR SDRAM
(Populated as 1 bank of x4 DDR SDRAM Module)
DQS9 (DM0)
D4 Q D5 Q D6 Q D7 Q
D0
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D9
DQS1
D8 Q D9 Q D1 Q0 D1 Q1 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS10 (DM1)
DQ12 DQ13 DQ14 DQ15
D1
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D10
DQS2
DQ16 DQ17 DQ18 DQ19 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS11 (DM2)
D2 Q0 D2 Q1 D2 Q2 D2 Q3
D2
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D11
DQS3
DQ24 DQ25 DQ26 DQ27 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS12 (DM3)
D2 Q8 D2 Q9 D3 Q0 D3 Q1
D3
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D12
DQS4
D3 Q2 D3 Q3 D3 Q4 D3 Q5 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS13 (DM4)
DQ36 DQ37 DQ38 DQ39
D4
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D13
DQS5
D4 Q0 D4 Q1 D4 Q2 D4 Q3 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS14 (DM5)
DQ44 DQ45 DQ46 DQ47
D5
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D14
DQS6
D4 Q8 D4 Q9 D5 Q0 D5 Q1 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS15 (DM6)
DQ52 DQ53 DQ54 DQ55
D6
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
Serial PD SCL WP A0 A1 SA1 A2 SA2 SDA
D15
DQS7
DQ56 DQ57 DQ58 DQ59 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS16 (DM7)
DQ60 DQ61 DQ62 D6 Q3
D7
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
SA0
D16
VDDSPD V DD /VDDQ
C S D M
DQS8
C0 B C1 B C2 B C3 B DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DQS17 (DM8)
C4 B C5 B C6 B C7 B
SPD D0 - D17 D0 - D17
D8
DS Q I/O 3 I/O 2 I/O 1 I/O 0
D17
VREF VS S
D0 - D17 D0 - D17 Strap: see Note 4
S0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R E G I S T E R
RS0_1 RS0_2 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0A RCKE0B RWE RESET BA0 -BA1 : SDRAMs DQ0 - D17 A0 -A12 : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS : SDRAMs DQ0 - D17 CKE : SDRAMs D0 - D8 CKE : SDRAMs D9 - D17 WE: SDRAMs D0 - D17
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
2GB, 256M x 72 ECC Module [ M383(12)L5628BT1(0) ] Functional Block Diagram
VSS RCS1 RCS0 DQS0
D0 Q D1 Q D2 Q D3 Q DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M D4 Q D5 Q D6 Q D7 Q
DDR SDRAM
(Populated as 2 bank of x4 DDR SDRAM Module)
DM0/DQS9
DS Q I/O 0 I/O 1 I/O 2 I/O 3 CS D M DS Q I/O 0 I/O 1 I/O 2 I/O 3 C S D M
D0
D18
D9
D27
DQS1
D8 Q D9 Q DQ10 DQ11 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM1/DQS10
D1 D19
DQ12 DQ13 DQ14 DQ15 DS Q I/O 0 I/O 1 I/O 2 I/O 3 CS D M
D10
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D28
DQS2
D1 Q6 D1 Q7 D1 Q8 D1 Q9 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM2/DQS11
D2 D20
DQ20 DQ21 DQ22 DQ23 DS Q I/O 0 I/O 1 I/O 2 I/O 3 CS D M
D11
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D29
DQS3
D2 Q4 D2 Q5 D2 Q6 D2 Q7 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM3/DQS12
D3
DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DQ28 DQ29 DQ30 DQ31
D21
DS Q I/O 0 I/O 1 I/O 2 I/O 3
CS
D M
D12
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D30
DQS4
DQ32 DQ33 DQ34 DQ35 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM4/DQS13
D4
DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M D3 Q6 D3 Q7 D3 Q8 D3 Q9
D22
DS Q I/O 0 I/O 1 I/O 2 I/O 3
CS
D M
D13
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D31
DQS5
DQ40 DQ41 DQ42 DQ43 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM5/DQS14
D5 D23
DQ44 DQ45 DQ46 DQ47 DS Q I/O 0 I/O 1 I/O 2 I/O 3 CS D M
D14
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D32
DQS6
DQ48 DQ49 DQ50 DQ51 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM6/DQS15
D6 D24
DQ52 DQ53 DQ54 DQ55 DS Q I/O 0 I/O 1 I/O 2 I/O 3 CS D M
D15
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D33
DQS7
DQ56 DQ57 DQ58 DQ59 DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM7/DQS16
D7
DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M DQ60 DQ61 DQ62 DQ63
D25
DS Q I/O 0 I/O 1 I/O 2 I/O 3
CS
D M
D16
DS Q I/O 0 I/O 1 I/O 2 I/O 3
C S
D M
D34
DQS8
C0 B C1 B C2 B C3 B DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S DM DS Q I/O 3 I/O 2 I/O 1 I/O 0 C S D M
DM8/DQS17
D8 D26
C4 B C5 B C6 B C7 B DS Q I/O 3 I/O 2 I/O 1 I/O 0 CS D M
D17
DS Q I/O 3 I/O 2 I/O 1 I/O 0
C S
D M
D35
V DDSPD Serial PD SCL WP A0
CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1
WE PCK PCK
SPD D0 - D35 D0 - D35
V D D /V DDQ SDA
A1 SA1
A2 SA2
VREF V SS
D0 - D35 D0 - D35
CK0, CK0 PLL
R E G I S T E R
RCS0 RCS1
RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE
SA0
BA0-BAn: SDRAMs D0 - D35 A0-An: SDRAMs D0 - D35 RAS: SDRAMs D0 - D35 CAS: SDRAMs D0 - D35 CKE: SDRAMs D0 - D17 CKE: SDRAMs D18 - D35 W SDRAMs D0 - D35 E:
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/ CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RESET
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol V IN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 * # of component 50
DDR SDRAM
Unit V V ?C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to V SS=0V, T A=0 to 70?C) Parameter Supply voltage(for device with a nominal V DD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;V OUT = VT T + 0.84V Output High Current(Normal strengh driver) ;V OUT = VT T - 0.84V Output High Current(Half strengh driver) ;V OUT = V T T + 0.45V Output High Current(Half strengh driver) ;V OUT = VT T - 0.45V Symbol VDD VDDQ V REF V TT V I H(DC) VIL(DC) V I N(DC) V I D(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 VDDQ/2-50mV V REF-0.04 VREF+0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ +0.3 V REF-0.15 VDDQ +0.3 VDDQ +0.6 2 5 V V V V V V V uA uA mA mA mA mA 3 1 2 4 4 Unit Note
Notes : 1. Includes ? ?25mV margin for DC offset on V REF, and a combined total of ??50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ? ?3nH. 2. V TT is not applied directly to the device. V T T is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM IDD spec table
M383(12)L6523BTS [ (64M x 8) * 9 , 512MB Module ]
DDR SDRAM
(V DD =2.7V, T = 10?C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A AA(DDR266@CL=2) 1,620 1,840 370 895 505 595 1,080 1,980 2,020 2,790 370 350 3,670 A2(DDR266@CL=2) 1,490 1,720 350 770 480 570 950 1,850 1,900 2,660 350 330 3,560 B0(DDR266@CL=2.5) 1,490 1,720 350 770 480 570 950 1,850 1,900 2,660 350 330 3,560 A0(DDR200@CL=2) 1,490 1,720 350 770 480 570 950 1,850 1,900 2,660 350 330 3,560 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M383(12)L2923BTS [ (64M x 8) * 18 , 1GB Module ]
(V DD =2.7V, T = 10?C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A AA(DDR266@CL=2) 2,190 2,420 540 1,290 810 990 1,650 2,550 2,600 3,360 540 500 4,260 A2(DDR266@CL=2) 2,190 2,420 540 1,290 810 990 1,650 2,550 2,600 3,360 540 500 4,260 B0(DDR266@CL=2.5) 2,190 2,420 540 1,290 810 990 1,650 2,550 2,600 3,360 540 500 4,260 A0(DDR200@CL=2) 2,190 2,420 540 1,290 810 990 1,650 2,550 2,600 3,360 540 500 4,260 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM IDD spec table
M383(12)L2920BTS [ (128M x 4) * 18 , 1GB Module ]
DDR SDRAM
(V DD=2.7V, T = 10?C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A AA(DDR266@CL=2) 2,610 3,010 420 1,170 690 870 1,530 3,330 3,420 4,950 420 380 6,750 A2(DDR266@CL=2) 2,610 3,010 420 1,170 690 870 1,530 3,330 3,420 4,950 420 380 6,750 B0(DDR266@CL=2.5) 2,610 3,010 420 1,170 690 870 1,530 3,330 3,420 4,950 420 380 6,750 A0(DDR200@CL=2) 2,610 3,010 420 1,170 690 870 1,530 3,330 3,420 4,950 420 380 6,750 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M383(12)L5628BT1(0) [ (st.256M x 4) * 18 , 2GB Module ]
(V DD=2.7V, T = 10?C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A AA(DDR266@CL=2) 3,760 4,210 760 1,960 1,300 1,660 2,680 4,480 4,570 6,100 760 680 7,900 A2(DDR266@CL=2) 3,760 4,210 760 1,960 1,300 1,660 2,680 4,480 4,570 6,100 760 680 7,900 B0(DDR266@CL=2.5) 3,760 4,210 760 1,960 1,300 1,660 2,680 4,480 4,570 6,100 760 680 7,900 A0(DDR200@CL=2) 3,760 4,210 760 1,960 1,300 1,660 2,680 4,480 4,570 6,100 760 680 7,900 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 Max
DDR SDRAM
Unit V V V V
Note 3 3 1 2
0.5*VDDQ+0.2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT =50? Output Z0=50? VREF =0.5*V DDQ
CLOAD =30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,W E ) Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK0 ) Input capacitance(DM0~DM8) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol Min CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 9 9 9 11 10 10 10
(VDD=2.5V, VDDQ=2.5V, TA= 25?C, f=1MHz) M383(12)L6523BTS, M383(12)L2920BTS Max 11 11 11 12 11 11 11 pF pF pF pF pF pF pF Unit
Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0,CKE1) Input capacitance( CS0, CS1) Input capacitance( CLK0, CLK0 ) Input capacitance(DM0~DM8) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7)
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2
M383(12)L2923BTS, M383(12)L5628BT1(0) Min 9 9 9 11 14 14 14 Max 11 11 11 12 16 16 16
Unit
pF pF pF pF pF pF pF
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/ CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR
AA (DDR266@CL=2) Min
60 75 45 15 15 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
A2 (DDR266@CL=2) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
B0 (DDR266@CL=2.5) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
A0 (DDR200@CL=2) Min
70 80 48 20 20 15 15 1 1 10 12 120K
Unit
ns ns ns ns ns ns ns tCK tCK ns ns
Note
Max
Max
Max
Max
0.45 0.45 -0.8 -0.8 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 1.1 1.1 -0.8 -0.8 0.5 0.5 1.0 0.67
0.55 0.55 +0.8 +0.8 0.6 1.1 0.6 1.25
tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK 3 12
1.1
tCK ns ns ns ns i,5.7~9 i,5.7~9 i, 6~9 i, 6~9 1 1
+0.8 +0.8
ns ns V/ns V/ns
4.5 1.5
V/ns
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
AA (DDR266@CL=2) Min
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL 0.4 20 (tWR/tCK) + tHP -tQHS tCLmin or tCHmin 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 0.75 0.6 0.4 20 (tWR/tCK) + tHP -tQHS tCLmin or tCHmin
DDR SDRAM
B0 (DDR266@CL=2.5) Min
15 0.5 0.5 2.2 1.75 7.5 75 200
Parameter
Symbol
A2 (DDR266@CL=2) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 0.75 0.6
A0 (DDR200@CL=2) Min
16 0.6 0.6 2.5 2 10 80 200
Unit
ns ns ns ns ns ns ns tCK
Note
Max
Max
Max
Max
j, k j, k 8 8
7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.4 20 (tWR/tCK) + 0.6 0.4 20 (tWR/tCK) + tHP -tQHS tCLmin or tCHmin
7.8 0.8 0.6
us ns ns ns tCK
4 11 10, 11 11 2
tCK
13
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR266 MIN TBD MAX TBD DDR200 MIN 0.5 MAX 4.0 Units V/ns Notes a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes i i i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes k k k
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps ps Notes j j j
DDR SDRAM
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR266 MIN TBD MAX TBD DDR200 MIN 0.67 MAX 1.5 NOTES e,m
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
DDR SDRAM
Test point Output 50? VSSQ Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ 50? Output Test point Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 ?C (T Ambient), VDDQ = 2.5V, typical process Minimum : 70 ?C (T Ambient), VDDQ = 2.3V, slow - slow process Maximum : 0 ?C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process v ariation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Table s 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tra nsi tions through the DC region must be monotony.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H H CKEn X X H L H X CS L L L L H L RAS L L L H X L
(V=Valid, X=Don?t Care, H=Logic High, L=Logic Low) CAS L L L H X H WE L L H H X H V BA0,1 A10/AP A0 ~ A9 A11, A12 Note 1, 2 1, 2 3 3 3 3
OP CODE OP CODE X
L H
X Row Address (A0~A9, A11,A12) L H L H X V X L H X
Column Address Column Address
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
H
X
L
H
L
H
V
4 4 4 4, 6 7
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
V
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA 1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Revison 1.0 December, 2003
512MB, 1GB, 2GB TSOP Registered DIMM
Physical Dimensions : 64M x 72 (M383L6523BTS)
DDR SDRAM
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950)
0.118 (3.00)
(2.30 Mi n)
0 .1 00 Min
A
B
0.39 3
REG
PLL
REG
2.500 A B
0.10 M C BA
(10 .0 0)
0.78 (19.80)
(17 .8 0)
0.7
(43 .3 3) 0.157 Max (3.99 Max) 0.050 0.0039 (1.270 0.10)
0.0787 R (2.00) 1.7 (0.167 ) ( 2.50 )
0.26 (6.62)
0.10 0
0.250 (6.350)
0.157 (4.00)
0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15)
0.118 (3.00)
0.1496 (3.80)
2.175
0.071 (1.80)
0.050 (1.270)
0.1575 (4.00) 0.10 M C AM B
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified. The used device is 64Mx8 DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H510838B
Revison 1.0 December, 2003
(4 .2 4)
512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM
Physical Dimensions: 128Mx72 (M383L2923BTS), 128Mx72 (M383L2920BTS)
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950) 0.118 (3.00)
(2.30 Min )
0.10 0 Min
A
B
0.393
REG
PLL
REG
2.500 A B
0.10 M C B A
( 10.00 )
0.78 (19.80)
(17.80 )
0.7
(0.16 7)
( 4.24)
0.050 0.0039 (1.270 0.10) 0.118 (3.00)
(2 .5 0 )
0.26 (6.62)
0.100
0.250 (6.350 )
0.157 (4.00 )
0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15)
0.1496 (3.80)
2.175
0.071 (1.80)
0.050 (1.270)
0.1575 (4.00) 0.10 M C AM B
Detail A Tolerances : 0.005(.13) unless otherwise specified. The used device is 64Mx8, 128Mx4, DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H510838B, K4H510438B
Detail B
Revison 1.0 December, 2003
(43.33 ) 0.157 Max (3.99 Max)
0.0787 R (2.00) 1.7
512MB, 1GB, 2GB TSOP Registered DIMM
Physical Dimensions: st.256Mx72 (M383L5628BT1)
DDR SDRAM
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950) 0.118 (3.00)
(2.30 Min )
0.10 0 Min
A
B
0.393
REG
PLL
REG
2.500 A B
0.10 M C BA
REG
( 10.00 )
0.78 (19.80)
(17.80 )
0.7
(43.33 ) 0.268 Max (6.81 Max) 0.050 0.0039 (1.270 0.10)
0.0787 R (2.00) 1.7 (0.16 7) (2 .5 0 ) 0.100
0.26 (6.62)
0.250 (6.350 )
0.157 (4.00 )
0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15)
0.118 (3.00)
0.1496 (3.80)
2.175
0.071 (1.80 )
0.050 (1.270)
0.1575 (4.00) 0.10 M C A M B
Detail A Tolerances : 0.005(.13) unless otherwise specified The used device is st.256Mx4 SDRAM, 66TSOPII SDRAM Part No. : K4H1G0638B
Detail B
Revison 1.0 December, 2003
(4 .2 4)
512MB, 1GB, 2GB TSOP Registered DIMM
Physical Dimensions : 64M x 72 (M312L6523BTS)
DDR SDRAM
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950)
0.118 (3.00)
PLL
(2.50 Mi n)
2.500 A B
0.10 M C B A
(2.30 Mi n)
0 .1 00 Min
A
B
(10 .0 0)
0.39 3
0.78 (19.80)
(17 .8 0) 0.157 Max ( 3.99 Max) 0.050 0.0039 (1.270 0.10)
( 0.157 )
REG
(4.00 )
( 2.50 )
0.26 (6.62)
0.10 0
0.250 (6.350)
0.157 (4.00)
0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15)
0.118 (3.00)
0.1496 (3.80)
2.175
0.071 (1.8 0)
0.050 (1.270 )
0.1575 (4.00) 0.10 M C AM B
Detail A Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8 DDR SDRAM, TSOPII SDRAM Part No : K4H510838B
Detail B
Revison 1.0 December, 2003
0.7
(30 .4 8)
0.0787 R (2.00)
REG
1.2
512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM
Physical Dimensions: 128Mx72 (M312L2923BTS), 128Mx72 (M312L2920BTS)
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950)
0.118 (3.00)
PLL
(2.50 Mi n)
2.500 A B
0.10 M C B A
(2 .3 0 Min)
0 .1 00 Min
A
B
(10 .0 0)
0.39 3
0.78 (19.80)
(17 .8 0) 0.157 Max ( 3.99 Max) 0.050 0.0039 (1.270 0.10)
( 0.157 )
REG
(4.00 )
( 2.50 )
0.10 0
0.26 (6.62)
0.250 (6.350)
0.157 (4.00)
0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15)
0.118 (3.00)
0.1496 (3.80)
2.175
0.071 (1.8 0)
0.050 (1.270 )
0.1575 (4.00) 0.10 M C AM B
Detail A Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDRSDRAM, TSOPII SDRAM Part No. : K4H510838B, K4H510438B
Detail B
Revison 1.0 December, 2003
0.7
(30 .4 8)
0.0787 R (2.00)
REG
1.2
512MB, 1GB, 2GB TSOP Registered DIMM
Physical Dimensions: st.256Mx72 (M312L5628BT0)
DDR SDRAM
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950)
0.118 (3.00)
(2.50 Mi n) (2.30 Min )
0 .1 00 Min
A
B
2.500 A B
0.10 M C B A 0.268 Max (6.81 Max)
( 0.157 )
(10 .0 0)
0.39 3
0.78 (19.80)
PLL
(4.00 )
(17 .8 0)
0.7
(30 .4 8) 0.050 0.0039 (1.270 0.10)
0.0787 R (2.00)
Reg.
1.2 ( 2.50 )
0.26 (6.62)
0.10 0
0.250 (6.350 )
0.157 (4.00 )
0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15)
0.118 (3.00)
0.1496 (3.80)
2.175
0.071 (1.80 )
0.050 (1.270)
0.1575 (4.00) 0.10 M C AM B
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is st.256Mx4 SDRAM, 66TSOPII SDRAM Part NO : K4H1G0638B
Revison 1.0 December, 2003

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